个人技术分享

1. Sequential Circuit 1

module top_module (
    input clk,
    input a,
    output q );
    
    always@(posedge clk)
        begin
           q <= ~a; 
        end

endmodule

2.  Sequential Circuit 2

module top_module (
    input clock,
    input a,
    output p,
    output q );
     
    always@(*)
        begin
            if(clock)
           		p <= a; 
        end
    
    always@(negedge clock)
        begin
           q <= p; 
        end

endmodule

3. Sequential Circuit 3

module top_module (
    input clk,
    input a,
    output reg [3:0] q );
     
    always@(posedge clk)
        begin
            if(a)
                q <= 4'd4;
            else if(q == 4'd6 )
                q <= 4'd0;
            else
                q <= q + 1;
        end

endmodule

4. Sequential Circuit 4

module top_module (
    input clk,
    input a,
    input b,
    output q,
    output state  );
    
    always@(posedge clk)
        begin
            if(a&b)
                state <= 1'b1;
            else if(~a&~b)
                state <= 1'b0;
            else
                state <= state;      
        end
    assign q = a^b^state;

endmodule