1. Lemmings 3
module top_module(
input clk,
input areset,
input bump_left,
input bump_right,
input ground,
input dig,
output walk_left,
output walk_right,
output aaah,
output digging
);
parameter left = 3'b0;
parameter right = 3'b1;
parameter d_left = 3'b10;
parameter d_right = 3'b11;
parameter f_left = 3'b100;
parameter f_right = 3'b101;
reg[2:0] state;
reg[2:0] next_state;
wire[1:0] bump;
assign bump = {bump_left,bump_right};
always @(*) begin
case (state)
left:begin
if (ground == 1'b0)
next_state = f_left;
else if(dig == 1'b1)
next_state = d_left;
else if((bump == 2'b10)||(bump == 2'b11))
next_state = right;
else
next_state = left;
end
right:begin
if (ground == 1'b0)
next_state = f_right;
else if(dig == 1'b1)
next_state = d_right;
else if((bump == 2'b01)||(bump == 2'b11))
next_state = left;
else
next_state = right;
end
d_left:begin
if(ground == 1'b0)
next_state = f_left;
else
next_state = d_left;
end
d_right:begin
if(ground == 1'b0)
next_state = f_right;
else
next_state = d_right;
end
f_left:begin
if(ground == 1'b0)
next_state = f_left;
else
next_state = left;
end
f_right:begin
if(ground == 1'b0)
next_state = f_right;
else
next_state = right;
end
endcase
end
always @(posedge clk or posedge areset) begin
if(areset)
state <= left;
else
state <= next_state;
end
assign walk_left = (state == left);
assign walk_right = (state == right);
assign digging = ((state == d_left)||(state == d_right));
assign aaah = ((state == f_left)||(state == f_right));
endmodule